Technical Field
The present disclosure generally relates to synchronous circuits. More particularly, but not exclusively, the present disclosure relates to methods and devices to manage at least one scan clock in synchronous circuits.
Description of the Related Art
Some circuits comprise hundreds of thousands of synchronous elements (e.g., flip flops) or more that share the same clock signal. For example, System on Chip (SoC) devices typically include large synchronous blocks of logic. Often, these circuits require testing. Testing methods may comprise a scan stage where values are propagated through the circuit on one or more clock pulses, and a capture stage where output values are obtained for analysis. These testing methods, particularly during SHIFT operations, pose challenges.
Many tests are designed to shift all of the flip flops in the device at the same time. During the shift, when all of the flip flops are clocked together, the large amount of switching causes a lot of current to be drawn from the power supply. Clock signal lines become susceptible to instantaneous voltage drop around the shift clock edges when too many devices are simultaneously clocked. Stated differently, due to an IR Drop during a scan shift operation, the device may undergo an instantaneous drop in the voltage around the shift clock edges below a minimum core signoff voltage. The instantaneous voltage drop will slow down clock and data signals, which creates skew between the signals, thus causing timing violations (setup/hold) and thereby leading to failures during the load and unload stages.
When a manufacturing production test indicates false failures, the false failures can have impact on the yield. Accordingly, manufacturers generally prefer to keep the IR Drop in all modes, including test modes, within the device functional mode limits for which signoff has been done. One determinative point in a logic scan is when all of the scan chain flip flops must are clocked during a Scan Shift stage in a test mode. A Scan Shift stage is unlike operations in a Functional Mode (e.g., a Scan Capture stage) where clock gating can be utilized to reduce the switching power. Instead, in a large SoC, a single clock domain may itself provide clock signals for most or all of the logic of the entire chip.
In one example, 80% of the flip flops belong to one single clock domain itself. In this case cases, IR drop management is challenging because all the flops will be clocked during the shift operation as they belong to a single clock domain. In the devices that use wire bond packages it will be even more critical than the flip chip.
To avoid problems with clock lines that are too heavily loaded, one conventional technique that is widely employed in the industry is to partition the large synchronous device and test only certain logic at a time. When one partition is being clocked, other partitions are switched off. In this technique, if there are two partitions, the entire synchronous device can be tested with a two pass strategy. Another solution is to toggle only a percentage of all the scan flops during the shift operation.
To carryout these conventional solutions, a large design is partitioned into smaller, manageable, hierarchical scan partitions. Each scan partition has its own compressor/decompressor. In order to reduce the Scan Stage IR drop during a shift operation and to also benefit the Capture Stage power, only one or a few scan partitions are tested at a time. In this way, switching activity is limited to a percentage of the total device flops, which prevents all of the flip flops from being clocked at the same. Thus, the logic of an entire chip can be tested by breaking the scan test into smaller tests targeting different scan partitions at different times. The entire chip is tested by breaking the scan test into smaller tests targeting different scan partitions at different times. In other words the complete device scan-based testing is serialized.
FIG. 1 shows a system on chip 10 with four clock domains, clock domain W 2, clock domain X 4, clock domain Y 6, and clock domain Z 6. Clock domain W is configured to receive an input clock W signal 12. Clock domain clock domain X is configured to receive an input clock X signal 14. Clock domain Y is configured to receive an input clock Y signal 16. Clock domain Z is configured to receive an input clock Z signal 18. Clock domains W, X, Y, and Z each comprise synchronous circuitry.
In some embodiments the clock domain Z may comprise much more circuitry than the other clock domains, alone or combined. For example, in some embodiments, the clock domain Z may comprise more than 80% of the total synchronous elements (e.g., flip flops) within the system on chip 10 and the clock domains W, X, and Y may comprise the remaining 20% or less of the synchronous circuitry.
In other embodiments, the system on chip may comprise only one clock domain. Some testing methods, for example, scan testing through Automatic Test Pattern Generation (ATPG), may require all the synchronous elements within a clock domain to be clocked on the same clock cycle. Clocking all synchronous elements on the same clock may not occur during the normal function of the circuitry, due for example to design consideration such as clock gating, but such testing may provide efficiency or useful information. Considering embodiments where the SoC comprises only one clock domain, clocking all synchronous elements in the SoC 10 on the same clock may result in the power requirement of the clock domain exceeding its design parameters, which may in turn result in an instantaneous voltage (or IR) drop across the clock domain. The instantaneous voltage drop may slow the clock and/or data signals which may create a skew between them and cause timing violations. These timing violations may lead to failures during load or unload stages and reduce the yield.
In order to address the possible timing violations, the SoC 10 of FIG. 1 is organized into multiple clock domains and multiple scan partitions. The SoC 10 executes the shift operation switching activity in two scan partitions. Synchronous devices (such as flip flops) belonging to clock domains W, X, and Y are grouped into a first scan partition Pwxy. A second scan partition Pz includes the synchronous devices of clock domain Z. Each of the two scan partitions has its own compressor/decompressor.
During the ATPG, one scan partition is enabled at a time. For example, during the first pass, the partition Pwxy of clock domains W, X, Y is active, while the second scan partition Pz is inactive. In a subsequent pass, the scan partition Pz is on while scan partition Pwxy is off. In this way, the entire device can be tested while the shift operation switching activity is controlled.